Monday, February 07, 2005


Ultra sonic Range Imager

This is the electronic schematic of the homebuilt SONAR. Only one piezoelectric tranducer is used for both tramsmit & receive. This transducer is switched from TX to RX via the four 4016 switches. A high gain amplifier stage & rectifier translates the received echoes into voltage pulses. The timing is controlled by the PIC12C508 8-pin microcontroller as it is shown in the following figure:


6

This is the electronic schematic of the homebuilt SONAR. Only one piezoelectric tranducer is used for both tramsmit & receive. This transducer is switched from TX to RX via the four 4016 switches. A high gain amplifier stage & rectifier translates the received echoes into voltage pulses. The timing is controlled by the PIC12C508 8-pin microcontroller as it is shown in the following figure:


5

Note that the graph is not drawn in a correct scale: The TX burst comprises 40 cycles (TX frequency of 40 KHz).
The SONAR system is connected to an analog input of a 68HC11 prototype board. The echos are sampled at about 18KHz, with 8 bit resolution. The captured data looks like this:


4

The starting decay is due to the residual trasducer oscilation. This decay limits the minimun range of the SONAR to about 50 cm. The peak around sample 230 is due to a wall echo. The wall was located 2.5m away from the SONAR. The next graph shows the echo of a close obstacle (me :) Two sucessive scans are shown:

Then, the SONAR was mechanically scanned with the help of an stepper motor controlled by the 68HC11. The transmited beam was also focused through a paper horn. The results were:


3

Another posibility for beam focusing is the use of lenses. The tested lens was of the Fresnel type. This lens was made on a PCB sustrate, and looks like:


2

The lens data were: Radius: 5.8 cm, Focus: 5 cm, Bands: 4. (HPGL file: lente.pgl) An sketch of the mechanical setup is here: sonar_mech.png
With the use of this lens the beam divergence was greatly reduced, but another problem arises: a notable fraction of the ultrasonic power is reflected back, causing undesired echoes that can be misinterpreted in the short range. The following graph shows the results obtained with the lens. The close echoes in the left are in fact back echoes. In the other hand, the distant echoes are a lot better resolved.


1

Tuesday, January 04, 2005

abstract

16-Bit Single Board Computer Design

Objective :

To evaluate the power quality when a number of Photovoltaic Power System are being tied to the grid and implement various applications using the using Intel 80C188EB Embedded Microprocessor

Methodology :

We are trying to evaluate the power quality by constructing a device for recording the distortion of AC voltage waveform. A method is to have FFT machine for computing Total Harmonic Distortion (THD).This can be done using Intel 80C188EB Embedded Microprocessor. The code can be tested with PC and then ported to the embedded board. While testing under PC, We can use printf for program debugging. However when running on C188, We will write the LCD functions that print result on LCD. The C188 has simple monitor program that allows user to download HEX file, examine memory, run the application program with special boot loader.

The C188SBC V1.0 features :

  • CPU: 80C188EB 16MHz
  • MEMORY: 29C040, 512kB Flash
  • 628512, 512kB battery backup SRAM
  • I/O: direct cpu bus interface 20x4 line LCD
  • 8-bit input port
  • 8-bit output port, 8-bit LPT, PS2 interface
  • MEMORY and I/O Decoder: GAL16V8D
  • RTC: DS12887
  • Debug LED: single dot LED connected to P1.7
  • Keypad: 4 tact switches
  • Host PC interface: RS232, 9600 8n1
  • I/O processor interface: half-duplex RS485
  • 10BaseT: Realtek RTL8019AS
  • Monitor Program: C188Bug V1.0

Hardware Schematic

Figure 2 shows the complete hardware schematic of the C188SBC V1.0. The CPU is 80C188EB25, 68-pin PLCC package. The chip has internal oscillator. We are using a 16MHz XTAL connected to CLKIN and OSCOUT pins. TP1 provides CLKOUT signal for peripheral. Reset signal produced by MAX691. TP2 also provides active high reset signal. The CPU has 20-bit address lines. The lower 8-bit lines are AD0-AD7, multiplex bus between A0-A7 and D0-D7. U2, 74HC573 with ALE control, latches A0-A7. The board has two memory chips, i.e. 512kB SRAM and 512kB Flash. Both chips needs A0-A18 to address 512kB space. The SRAM was selected by LCS (lower memory chip select) and the Flash by UCS (upper chip select). In this design the PLD was not used to decode memory chip.

Figure 3: 1MB Memory Map

When power up reset, the CS register will be FFFFH and the IP will be 0000H, the physical address that sends out to the memory will then be FFFF0H. The UCS actives low to select the Flash memory for first instruction to be fetched. Since the CPU has internal programmable chip select unit, so we do not need external memory decoder. The Flash memory can be 64kB(29C512), 128kB(29C010), 256kB(29C020) or 512kB(29C040). We can use such memory chips plugged into U16 socket without any modifications. For example, it we use 64kB Flash, 29C512, then the reset vector appeared in the chip will be FFF0H. When put it on the board, it will be seen by CPU at FFFF0H.

The LCS was programmed by monitor program to

be activated from address 00000H-7FFFFH (first 512kB).

U6 is PLD used for I/O space decoder. The onboard I/O uses GCS6 which was programmed to be activated for I/O space from location 3000H to 3FFFH. A8-A10 provides 8-location. Figure 4 shows the I/O map. GPIO1 and GPIO2 shares the same location but GPIO1 is for input port and GPIO2 for output port. The onboard I/O devices use buffered data bus through U1, tristate transceiver. The IOEX signal was enabled when GCS3-GCS6 are active.

Figure 4: I/O Map with GCS6

U15, 75176 standard RS485 bus transceiver ties to the on chip UART channel1. The UART channel 0 is for terminal interface. Figure 5 shows the Flash and SRAM under LCD. In this design, We are not using bus status, S0 S1 S2 to decode I/O space, since the number of input pins is not enough. Instead we are using preprogrammed GCS6 to select I/O space.

And each of us are trying to develop four separate applications.



Monday, January 03, 2005

J51 Java 8051 emulator

J51 Java 8051 emulator

Monday, December 27, 2004

80186 In Circuit Emulator

80186 In Circuit Emulator

Intel Corporation - U.S. Site Index

Intel Corporation - U.S. Site Index

Eric Rollins

Eric Rollins: "a Jabber Internet two-player Hex game"

Starware Search: projects on intel 80C188

Starware Search: projects on intel 80C188

Projects on 80c188

Tuesday, December 21, 2004

Build Your Own Microcontroller Projects

Build Your Own Microcontroller Projects

Build Your Own Microcontroller Projects

Build Your Own Microcontroller Projects